Target Addressing (B-Operand) and Remote Memory Mutation
How modifying the destination offset lets an instruction reach across space to mutate distant memory cells
Now let's keep the added amount (A = #5) as-is, and change where it gets added (B)! Currently 0000 is ADD.AB #5, $1, which adds 5 to Cell 0001 (1 row down).
🎯 Your Task Change the highlighted B (Right Value) of 0000 from $1 to $2 (2 rows down), then press [STEP] so Cell 0002's B-value becomes 5!
1. The B-Field as the Spatial Target Coordinate
In Step 9, you kept the added amount fixed at #5 and changed the right-hand room (B-field) of Address 0000 from "$1" to "$2". Immediately, the green target arrow vaulted over Cell 0001 to point directly at Cell 0002. When you pressed [STEP], Cell 0001 remained untouched at 0 while Cell 0002's B-value jumped to 5.
Comparing Step 8 and Step 9 side by side reveals the clean symmetry of machine code: - In Step 8 (modifying A), you changed HOW MUCH energy was delivered (#1 ➔ #5) to the same box. - In Step 9 (modifying B), you changed WHERE that energy was delivered ($1 ➔ $2) across memory space.
While the A-field governs the magnitude of the operation, the B-field governs its spatial reach. Together, these two fields give every arithmetic instruction a complete vector description: "What quantity to apply" (A) and "Which coordinate in memory space to apply it to" (B). By separating the operational payload from the spatial target address, a programmer can retarget an algorithm to act upon any variable or data structure in memory simply by adjusting a single offset number.
[0000] ADD.AB #5, $2 ──┐
[0001] DAT.F #0, #0 │ (Bypassed! Untouched at 0)
[0002] DAT.F #0, #5 ◄─┘ (Target $2 = 0000 + 2: B-value becomes 5)2. The CPU Address Bus and Random Access Memory (RAM)
How can an instruction sitting at Address 0000 reach directly into Address 0002 without passing through or disturbing Address 0001 in between?
The answer is captured in the very name of computer memory: RAM, which stands for Random Access Memory. In computer science, "random access" does not mean arbitrary or chaotic; it means that the processor can access ANY memory address directly in the exact same amount of time, regardless of its physical distance from the current instruction.
In early sequential-access storage media like magnetic tape, reaching a piece of data 500 blocks away required physically spooling the tape past all 499 intermediate blocks. In RAM, by contrast, the CPU is connected to memory via an Address Bus—a parallel bundle of wires that acts like a coordinate grid. Whether your B-field specifies "$1" (1 cell away), "$2" (2 cells away), or "$400" (halfway across the arena), the address decoder activates that exact memory cell's circuit line in a single clock cycle. This constant-time spatial reach is what makes RAM the universal canvas of modern computing: an instruction at the top of memory can effortlessly sculpt data structures at the bottom of memory without ever moving its own position.
3. Hardware Offset Calculation: Effective Address = PC + Offset
Whenever the MARS processor encounters a direct relative operand like "$2", its address generation unit computes what computer architects call the Effective Address using a simple formula: Effective Address = (Current Program Counter + Relative Offset) mod CoreSize
In Step 9, your instruction executed at Address 0000 (PC = 0) with an offset of +2, yielding an Effective Address of 0 + 2 = 0002. If that exact same instruction ("ADD.AB #5, $2") were placed at Address 0010, its Effective Address would automatically become 10 + 2 = 0012. Always count relative offsets starting from the executing line itself as zero ($0). Notice how the workbench's green predictive arrow automatically performs this Effective Address calculation for you at Cycle 0: as you increment the B-field from $1 to $2, $3, or $4, the arrow tip walks down the memory column row by row. This visual feedback mirrors the dedicated Address Generation Unit (AGU) inside modern CPUs, which computes target memory coordinates in parallel with main ALU operations so that data fetches and writes occur without delay.
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