Anatomy of a Machine Instruction Word: Opcode, A-Field, and B-Field
Why every memory cell is divided into three distinct rooms, and how fixed-length instruction words simplify CPU hardware design
Look at the column headers at the top of the memory view. Every single memory row in CoreWar is divided into three rooms: 1. [Opcode]: What action to perform (DAT, ADD, MOV, etc.) 2. [A (Left Value)]: The left-hand number (A-field) 3. [B (Right Value)]: The right-hand number (B-field)
The B (Right Value) room is most commonly used to store data values.
🎯 Your Task Change ONLY the B (Right Value) of DAT #0, #0 at Address 0000 to 5, then press [STEP]!
1. Every Memory Row Is a Structured Machine Word
In Step 4, you explored the internal layout of a single memory cell—divided into three distinct rooms: Opcode, A (Left Value), and B (Right Value)—and set the B-field of Address 0000 to 5.
Beginners encountering assembly language for the first time often wonder: "Why is memory rigidly partitioned into these specific slots instead of letting us write free-form text like a normal document?"
The answer lies in the physical nature of digital hardware. While a human brain can parse flexible sentences of varying lengths, a CPU's instruction decoder is built from physical logic gates and wires. If every memory cell follows a strict, uniform blueprint—Slot 1 for the operation type (Opcode), Slot 2 for the first operand (A-field), and Slot 3 for the second operand (B-field)—the hardware can route each piece of information directly into the Arithmetic Logic Unit (ALU) in a single clock cycle without wasting time guessing where one piece of data ends and another begins.
┌─────────────────────────────────────────────────────────────┐
│ 1 Memory Cell (ICWS-94 Instruction Word) │
├───────────────────┬────────────────────┬────────────────────┤
│ Room 1: OPCODE │ Room 2: A-FIELD │ Room 3: B-FIELD │
│ (Action + Mod) │ (Mode + A-Value) │ (Mode + B-Value) │
│ DAT.F │ #0 │ #5 │
└───────────────────┴────────────────────┴────────────────────┘2. RISC Architecture and the Elegance of Fixed-Length Words
In the history of computer architecture, two major design philosophies have competed for dominance. The first is CISC (Complex Instruction Set Computer), exemplified by Intel's x86 architecture, where instructions vary wildly in length from 1 byte to 15 bytes. The second is RISC (Reduced Instruction Set Computer), which powers ARM processors, Apple Silicon, and RISC-V. In a classic RISC design, every single instruction occupies the exact same fixed width (typically one 32-bit word).
CoreWar's virtual machine (MARS, governed by the ICWS-94 standard) is the ultimate expression of fixed-length architectural purity. In CoreWar, every memory address—from 0000 to 0799—holds exactly one complete instruction word consisting of an Opcode (with its modifier), an A-operand, and a B-operand.
Because every instruction and every data item occupies the exact same unit of space (one cell), the Program Counter never has to calculate variable byte offsets to find the next instruction—it simply increments by 1. Even more importantly, a single MOV instruction can copy any instruction in the universe in one atomic step. If instructions had variable byte lengths like x86, copying an instruction or jumping backward would require counting exact byte boundaries, and jumping into the middle of a multi-byte instruction would corrupt the instruction stream. Uniform 1-cell words make self-replication and pointer math clean and predictable.
3. Why the B-Field (Right Room) Is the Primary Data Slot
In this exercise, we specifically stored the number 5 inside the B-field (the right-hand room) rather than the A-field. Throughout CoreWar and the Redcode-94 standard, there is a universal convention: when a DAT cell is used to hold a single numerical variable, counter, or pointer offset, that number is stored in the B-field.
Why the B-field instead of the A-field? As you will discover in upcoming steps, standard arithmetic instructions (like ADD.AB) and indirect pointer modes (like @ and <) are hardwired by default to treat the A-field as the incoming source value and the B-field of the target cell as the destination accumulator or pointer address. By keeping your primary data in the right-hand room (B), all standard Redcode instructions naturally align with your data boxes. This convention also makes inspecting memory during debugging much faster: whenever your eyes scan down the rightmost column of the workbench or the Memory Inspector, you are looking directly at the active counters, bomb payloads, and target pointers of the program. Building this habit early will make dissecting complex warriors effortless.
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